The inventive concepts relate to an inspection method, an inspection system, and a method of fabricating a fan-out package using the same.
Sizes of semiconductor chips becomes smaller with high integration of the semiconductor chip. However, the intervals between bumps on a semiconductor chip are fixed by an international standard of an international electronics standardization organization, the Joint Electronic Device Engineering Council (JEDEC). Bonding a desired number of the bumps to the semiconductor chip may thus be difficult. In addition, as the size of the semiconductor chip becomes reduced, handling and testing the semiconductor chips become more difficult. Additionally, problems of acquiring diversified mount boards in accordance with the size of the semiconductor chip occur. In order to mitigate or improve on the problems above, a fan-out package has been developed.
A fan-out packaging process may include forming insulation layers and routing lines on a substrate on which a semiconductor chip is mounted. The routing lines may include variously shaped patterns, and a highly accurate inspection method is required to minimize or reduce defects occurred on the various shaped patterns.